1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method. More specifically, the present invention relates to a method for forming a gate dielectric of a semiconductor device.
2. Description of the Related Art
Among various manufacturing technologies of semiconductor devices, a system on chip (SOC) device equipped with memory elements and large scale integrated circuits (LSI) on a single chip has been recently developed. In SOC devices, various circuit elements, such as a processor, controller, memory device, etc., are integrated in a single chip, while such circuit elements are also conventionally formed in separate chips to be individually mounted on a printed circuit board (PCB). The SOCs have advantages in aspects of miniaturization, operational speed, low power consumption, and so on. In general, SOCs comprise a variety of transistors having a large range of operational voltages and metal oxide semiconductor (MOS) capacitors having a great capacity, wherein each transistor or capacitor includes one or more dielectric layers for use as a gate dielectric.
Conventionally, a high-temperature heat treatment is used in formation of a gate dielectric in the SOCs. However, the high-temperature heat treatment may affect a junction or well profile formed in a semiconductor substrate, thus resulting in a risk of deterioration of reliability in manufacturing processes. Moreover, dopant ions implanted in the substrate may diffuse into the dielectric during the heat treatment, which may induce gate depletion and current leakage problems.